A new settling-time-oriented design strategy for two-stage operational amplifiers with current-buffer Miller compensation is presented. The proposed approach defines a systematic procedure to optimize the amplifier time response, allowing the required speed performances to be achieved without both power wasting and blind efforts for time-consuming trial-and-error design processes. To demonstrate the effectiveness of the methodology, a design example in a commercial 0.35 μm CMOS technology is presented. As shown by circuit and statistical simulations, the proposed strategy proves to be very useful to develop fast-settling operational amplifiers for typical discrete-time applications, such as switched-capacitor filters and ΣΔ analog-to-digital converters.