You have Guest access.
Log In
Volume 1 / 1990 - Volume 27 / 2011
567-568
Editorial Board
Editorial
Vishwani D. Agrawal
569-570
Test Technology Technical Council Newsletter
571-581
Structural Fault Based Specification Reduction for Testing Analog Circuits
Soon-Jyh Chang, Chung Len Lee and Jwu E. Chen
583-594
Fast Anti-Random (FAR) Test Generation to Improve the Quality of Behavioral Model Verification
Tom Chen, Andre Bai, Amjad Hajjar, Anneliese K. Amschler Andrews and C. Anderson
595-611
Behavioral-Level DFT via Formal Operator Testability Measures
Sandhya Seshadri and Michael S. Hsiao
613-626
Partial Scan Testing on the Register-Transfer Level
Bruce S. Greene and Samiha Mourad
627-636
An Interleaving Technique for Reducing Peak Power in Multiple-Chain Scan Circuits During Test Application
Kuen-Jong Lee and Tsung-Chu Huang
637-647
A Built-in Self-Test Scheme with Diagnostics Support for Embedded SRAM
Chih-Wea Wang, Chi-Feng Wu, Jin-Fu Li, Cheng-Wen Wu and Tony Teng, et al.
649-660
Authors Index
2002 Annual Index
Frequently asked questions General info on journals and books Send us your feedback Impressum Contact us
© Springer, Part of Springer Science+Business Media Privacy, Disclaimer, Terms & Conditions, and Copyright Info