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Volume 1 / 1990 - Volume 27 / 2011
95
Editorial Introduction
Editorial
Vishwani D. Agrawal
97-98
Editorial Board
New Editorial Board Members
99-100
Test Technology Technical Council Newsletter
André Ivanov
101-102
Guest Editorial
103-112
Instruction-Based Self-Testing of Processor Cores
Nektarios Kranitis, Antonis Paschalis, Dimitris Gizopoulos and Yervant Zorian
113-123
LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects
Krishna Sekar and Sujit Dey
125-135
Modern Test Techniques: Tradeoffs, Synergies, and Scalable Benefits
Erik H. Volkerink, Ajay Khoche, Jochen Rivoir and Klaus D. Hilliges
137-147
Performance Comparison of VLV, ULV, and ECR Tests
Wanli Jiang and Eric Peterson
149-160
A Hierarchical Test Generation Approach Using Program Slicing Techniques on Hardware Description Languages
Vivekananda M. Vedula, Jacob A. Abraham, Jayanta Bhadra and Raghuram Tupuri
161-172
A Symbolic Inject-and-Evaluate Paradigm for Byzantine Fault Diagnosis
Shi-Yu Huang
173-182
Statistical Tolerance Analysis for Assured Analog Test Coverage
Sule Ozev and Alex Orailoglu
183-193
Timing Jitter Measurement of Intrinsic Random Jitter and Sinusoidal Jitter Using Frequency Division
Takahiro J. Yamaguchi, Masahiro Ishida, Mani Soma, Louis Malarsie and Hirobumi Musha
195-205
Dynamic Faults in Random-Access-Memories: Concept, Fault Models and Tests
Said Hamdioui, Zaid Al-Ars, Ad J. van de Goor and Mike Rodgers
207-215
Testing and Diagnosis Methodologies for Embedded Content Addressable Memories
Jin-Fu Li, Ruey-Shing Tzeng and Cheng-Wen Wu
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