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Volume 1 / 1990 - Volume 27 / 2011
219
Editorial Board
Editorial
Vishwani D. Agrawal
221-222
Test Technology Technical Council Newsletter
A. Ivanov
223-231
A Ring Architecture Strategy for BIST Test Pattern Generation
C. Fagot, O. Gascuel, P. Girard and C. Landrault
233-244
LFSR Characteristic Polynomials for Pseudo-Exhaustive TPG with Low Number of Seeds
Dimitri Kagaris and Spyros Tragoudas
245-269
Built-in Test with Modified-Booth High-Speed Pipelined Multipliers and Dividers
Hao-Yung Lo, Hsiu-Feng Lin, Chichyang Chen, Jenshiuh Liu and Chia-Cheng Liu
271-284
Modeling Fault Coverage of Random Test Patterns
Hailong Cui, Sharad C. Seth and Shashank K. Mehta
285-298
Easily Testable Cellular Carry Lookahead Adders
Dimitris Gizopoulos, Mihalis Psarakis, Antonis Paschalis and Yervant Zorian
299-314
A DFT Technique for Testing High-Speed Circuits with Arbitrarily Slow Testers
Muhammad Nummer and Manoj Sachdev
315-324
A Novel Built-In Self-Repair Approach for Embedded RAMs
Shyue-Kung Lu
325-340
Replacing IDDQ Testing: With Variance Reduction
C. Thibeault
341-352
Leakage Current in Sub-Quarter Micron MOSFET: A Perspective on Stressed Delta IDDQ Testing
Oleg Semenov, Arman Vassighi and Manoj Sachdev
353-357
Thermal Testing of Analogue Integrated Circuits: A Case Study
J. Altet, A. Ivanov and A. Wong
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