You have Guest access.
Log In
Volume 1 / 1990 - Volume 27 / 2011
127
Editorial Introduction
Editorial
Vishwani D. Agrawal
129-130
Editorial Board
New Editorial Board Members
131-132
Test Technology Technical Council Newsletter
P. Prinetto
133-142
A Design for Testability Scheme for CMOS LC-Tank Voltage Controlled Oscillators
L. Dermentzoglou, Y. Tsiatouhas and A. Arapoyanni
143-153
Analog Switches in Programmable Analog Devices: Quiescent Defective Behaviours
R. Rodríguez-Montañés, D. Muñoz, L. Balado and J. Figueras
155-168
A Low-Cost At-Speed BIST Architecture for Embedded Processor and SRAM Cores
M.H. Tehranipour, S.M. Fakhraie, Z. Navabi and M.R. Movahedin
169-179
Testability Trade-Offs for BIST Data Paths
Nicola Nicolici and Bashir M. Al-Hashimi
181-197
Scalable Delay Fault BIST for Use with Low-Cost ATE
Ilia Polian and Bernd Becker
199-212
Analysis of Test Application Time for Test Data Compression Methods Based on Compression Codes
Anshuman Chandra and Krishnendu Chakrabarty
213-216
Scan Latch Design for Test Applications
Amit M. Sheth and Jacob Savir
Frequently asked questions General info on journals and books Send us your feedback Impressum Contact us
© Springer, Part of Springer Science+Business Media Privacy, Disclaimer, Terms & Conditions, and Copyright Info