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Volume 1 / 1990 - Volume 27 / 2011
571
Editorial
Vishwani D. Agrawal
573-574
List of Reviewers
575-589
Using RT Level Component Descriptions for Single Stuck-at Hierarchical Fault Simulation
Zainalabedin Navabi, Shahrzad Mirkhani, Meisam Lavasani and Fabrizio Lombardi
591-609
Modeling Custom Digital Circuits for Test
Soumitra Bose
611-622
A Signature Analysis Technique for the Identification of Failing Vectors with Application to Scan-BIST*
Michael Goessel, Krishnendu Chakrabarty, Vitalij Ocheretnij and Andreas Leininger
623-638
A Built-in-Self-Test Scheme for Segmented and Binary Weighted DACs
Sunil Rafeeque K.P. and Vinita Vasudevan
639-645
Scan Test Strategy for Asynchronous-Synchronous Interfaces
Octavian Petre and Hans G. Kerkhoff
647-660
Power-Driven Routing-Constrained Scan Chain Design
Y. Bonhomme, P. Girard, L. Guiller, C. Landrault and S. Pravossoudovitch
661-665
Area Minimization of Exclusive-OR Intensive Circuits in FPGAs
Seok-Bum Ko
667-670
On Using Exponential-Golomb Codes and Subexponential Codes for System-on-a-Chip Test Data Compression
Lei Li and Krishnendu Chakrabarty
671-681
2004 Annual Index
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