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Volume 1 / 1990 - Volume 27 / 2011
5
Editorial
Vishwani D. Agrawal
7-8
New Editorial Board Members
9-16
A Strategy for Optimal Test Point Insertion in Analog Cascaded Filters
F. Azaïs, M. Lubaszewski, P. Nouet and M. Renovell
17-31
Optimal Interconnect ATPG Under a Ground-Bounce Constraint
Henk D. L. Hollmann, Erik Jan Marinissen and Bart Vermeulen
33-42
EEPROM Diagnosis Based on Threshold Voltage Embedded Measurement
J. M. Portal, H. Aziza and D. Née
43-55
Delay Fault Testing of Look-Up Tables in SRAM-Based FPGAs
Patrick Girard, Olivier Héron, Serge Pravossoudovitch and Michel Renovell
57-69
Modeling Feedback Bridging Faults with Non-Zero Resistance
Ilia Polian, Piet Engelke, Michel Renovell and Bernd Becker
71-82
A New Testability Calculation Method to Guide RTL Test Generation
Jaan Raik, Tanel Nõmmeots and Raimund Ubar
83-93
A Degree-of-Freedom Based Synthesis Scheme for Sequential Machines with Enhanced BIST Quality and Reduced Area
Biplab K. Sikdar, S. Roy and Debesh K. Das
95-107
Design of Nonlinear CA Based TPG Without Prohibited Pattern Set In Linear Time
Sukanta Das, Anirban Kundu, Biplab K. Sikdar and P. Pal Chaudhuri
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