Special Issue on On-Line-Testing and Fault Tolerance
Guest Editors: Ceceilia Metra and Régis Leveugle
343
Editorial
345
Test Technology Newsletter
347
Guest Editorial
349-363
Fault Modeling and Simulation of Power Supply Voltage Transients in Digital Systems on a Chip
D. Barros Júnior, M. Rodriguez-Irago, M. B. Santos, I. C. Teixeira and F. Vargas, et al.
365-376
Combined Fault Classification and Error Propagation Analysis to Refine RT-Level Dependability Evaluation
A. Ammari, K. Hadjiat and R. Leveugle
377-389
Self-Checking Voter for High Speed TMR Systems
José Manuel Cazeaux, Daniele Rossi and Cecilia Metra
391-404
Single- and Double-Output Embedded Checker Architectures for Systematic Unordered Codes∗
Steffen Tarnick
405-416
The Integration of On-Line Monitoring and Reconfiguration Functions into a Safety Critical Automotive Electronic Control Unit
C. Jeffrey, R. Cutajar, A. Richardson, S. Prosser and M. Lickess, et al.
417-427
Low Cost On-Line Testing Strategy for RF Circuits
Marcelo Negreiros, Luigi Carro and Altamiro A. Susin
429-444
A Comparative Evaluation of Designs for Reliable Memory Systems
G. C. Cardarilli, F. Lombardi, M. Ottavi, S. Pontarelli and M. Re, et al.
445-455
Memory Defect Tolerance Architectures for Nanotechnologies
Michael Nicolaidis, Lorena Anghel and Nadir Achouri