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Volume 1 / 1990 - Volume 27 / 2011
5
Editorial
Vishwani D. Agrawal
7
New Editor
9-10
Test Technology Newsletter The Newsletter of the Test Technology Technical Council of the IEEE Computer Society
Bruce C. Kim
11-24
Improve the Quality of Per-Test Fault Diagnosis Using Output Information
Chunsheng Liu
25-34
Magnetic In-circuit Testing of Multiple Power and Ground Pins for Open Faults
Uğur Çilingiroğlu
35-45
Isolation of Failing Scan Cells through Convolutional Test Response Compaction
Grzegorz Mrugalski, Janusz Rajski, Chen Wang, Artur Pogiel and Jerzy Tyszer
47-54
Evaluating Different Solutions to Design Fault Tolerant Systems with SRAM-based FPGAs
L. Sterpone, M. Sonza Reorda, M. Violante, F. Lima Kastensmidt and L. Carro
55-74
Minimal March Tests for Detection of Dynamic Faults in Random Access Memories
G. Harutunyan, V. A. Vardanian and Y. Zorian
75-84
Generation of Primary Input Blocking Pattern for Power Minimization during Scan Testing
Wang-Dauh Tseng
85-94
RF Testing on a Mixed Signal Tester
Dana Brown, John Ferrario, Randy Wolf, Jing Li and Jayendra Bhagat, et al.
95-106
A Low-Cost Test Methodology for Dynamic Specification Testing of High-Speed Data Converters
Shalabh Goyal, Abhijit Chatterjee and Michael Purtell
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