Special Issue on Defect and Fault Tolerance; Guest Editors: Nur A. Touba, Adelio Salsano, and Minsu Choi
1
Editorial
Vishwani D. Agrawal
3-4
New Editors
5-6
Test Technology Newsletter February 2008
The Newsletter of the Test Technology Technical Council of the IEEE Computer Society
7-8
List of 2007 Reviewers
9-10
Guest Editorial
Nur Touba, Adelio Salsano and Minsu Choi
11-19
Circuit and Latch Capable of Masking Soft Errors with Schmitt Trigger
Yoichi Sasaki, Kazuteru Namba and Hideo Ito
21-33
Error Detection Enhancement in PowerPC Architecture-based Embedded Processors
Mahdi Fazeli, Reza Farivar and Seyed Ghassem Miremadi
35-44
Software and Hardware Techniques for SEU Detection in IP Processors
C. Bolchini, A. Miele, M. Rebaudengo, F. Salice and D. Sciuto, et al.
45-56
Hardware and Software Transparency in the Protection of Programs Against SEUs and SETs
Eduardo Luis Rhod, Carlos Arthur Lang Lisbôa, Luigi Carro, Matteo Sonza Reorda and Massimo Violante
57-65
A New Approach to Single Event Effect Tolerance Based on Asynchronous Circuit Technique
Rui Gong, Wei Chen, Fang Liu, Kui Dai and Zhiying Wang
67-81
Design of Low Power & Reliable Networks on Chip Through Joint Crosstalk Avoidance and Multiple Error Correction Coding
Amlan Ganguly, Partha Pratim Pande, Benjamin Belzer and Cristian Grecu
83-92
Majority Logic Mapping for Soft Error Dependability
Lorenzo Petroli, Carlos Arthur Lang Lisboa, Fernanda Lima Kastensmidt and Luigi Carro
93-103
Checkers’ No-Harm Alarms and Design Approaches to Tolerate Them
Daniele Rossi, Martin Omaña and Cecilia Metra
105-116
Analysis and Evaluations of Reliability of Reconfigurable FPGAs
Salvatore Pontarelli, Marco Ottavi, Vamsi Vankamamidi, Gian Carlo Cardarilli and Fabrizio Lombardi, et al.
117-128
Hierarchical Verification for Increasing Performance in Reliable Processors
Joonhyuk Yoo and Manoj Franklin
129-141
Performance-Optimized Design for Parametric Reliability
Ramyanshu Datta, Jacob A. Abraham, Abdulkadir Utku Diril, Abhijit Chatterjee and Kevin J. Nowka
143-155
Design Considerations for High Performance RF Cores Based on Process Variation Study
Shambhu Upadhyaya, Nandakumar P. Venugopal, Nihal Shastry, Srinivasan Gopalakrishnan and Bharath V. Kuppuswamy, et al.
157-163
Improving Yield and Defect Tolerance in Subthreshold CMOS Through Output-Wired Redundancy
Kristian Granhaug and Snorre Aunet
165-179
Defect Analysis and Defect Tolerant Design of Multi-port SRAMs
Lushan Liu, Pradeep Nagaraj, Shambhu Upadhyaya and Ramalingam Sridhar
181-192
A Built-In Redundancy-Analysis Scheme for Random Access Memories with Two-Level Redundancy
Da-Ming Chang, Jin-Fu Li and Yu-Jen Huang
193-201
Substrate Testing on a Multi-Site/Multi-Probe ATE
Xiaojun Ma and Fabrizio Lombardi
203-222
On the Use of ZBDDs for Implicit and Compact Critical Path Delay Fault Test Generation
Kyriakos Christou, Maria K. Michael and Spyros Tragoudas
223-233
Adaptive Fault Diagnosis of Analog Circuits by Operation-Region Model and
X
–
Y
Zoning Method
Yukiya Miura and Jiro Kato
235-246
Scan Test Response Compaction Combined with Diagnosis Capabilities
Sverre Wichlund, Frank Berntsen and Einar Johan Aas
247-257
Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving
Zhiyuan He, Zebo Peng, Petru Eles, Paul Rosinger and Bashir M. Al-Hashimi
259-269
A Methodology for Handling Complex Functional Constraints for Large Industrial Designs
Abhijit Jas, Yi-Shing Chang and Sreejit Chakravarty
271-284
Monomer Control for Error Tolerance in DNA Self-Assembly
Byunghyun Jang, Yong-Bin Kim and Fabrizio Lombardi
285-296
Bilateral Testing of Nano-scale Fault-Tolerant Circuits
Lei Fang and Michael S. Hsiao
297-311
Reversible Gates and Testability of One Dimensional Arrays of Molecular QCA
X. Ma, J. Huang, C. Metra and F. Lombardi
313-320
Scalability of Globally Asynchronous QCA (Quantum-Dot Cellular Automata) Adder Design
Myungsu Choi and Minsu Choi