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Volume 1 / 1990 - Volume 27 / 2011
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Iterative Antirandom Testing
Ireneusz Mrozek and Vyacheslav N. Yarmolik
Online First™, 10 January 2012
A DfT Architecture for 3D-SICs Based on a Standardizable Die Wrapper
Erik Jan Marinissen, Chun-Chuan Chi, Mario Konijnenburg and Jouke Verbree
Online First™, 12 December 2011
Test Impact on the Overall Die-to-Wafer 3D Stacked IC Cost
Mottaqiallah Taouil, Said Hamdioui, Kees Beenakker and Erik Jan Marinissen
Online First™, 7 December 2011
Scheduling Tests for 3D Stacked Chips under Power Constraints
Breeta SenGupta, Urban Ingelsson and Erik Larsson
Online First™, 9 September 2011
Fault Diagnosis with Orthogonal Compactors in Scan-Based Designs
Brady Benware, Grzegorz Mrugalski, Artur Pogiel, Janusz Rajski and Jędrzej Solecki, et al.
2011, Volume 27, Number 5, Pages 599-609
Bandwidth Analysis of Functional Interconnects Used as Test Access Mechanism
Ardy van den Berg, Pengwei Ren, Erik Jan Marinissen, Georgi Gaydadjiev and Kees Goossens
2010, Volume 26, Number 4, Pages 453-464
A Better Method than Tail-fitting Algorithm for Jitter Separation Based on Gaussian Mixture Model
Fangyuan Nan, Yaonan Wang, Fuhai Li, Weifeng Yang and Xiaoping Ma
2009, Volume 25, Number 6, Pages 337-342
A Reconfigurable Power Conscious Core Wrapper and its Application to System-on-Chip Test Scheduling
Erik Larsson and Zebo Peng
2008, Volume 24, Number 5, Pages 497-504
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