We are interested in the automatic verification of digital designs specified in the popular hardware description language VHDL. This paper presents a static analysis that computes a superset of the states maybe reached during the simulation of a VHDL design. We follow the methodology of abstract interpretation. To model the execution of a VHDL description, we first define a concise structural operational semantics. Our analysis is then derived by abstraction from this formal model. It is designed so as to be parametric in the representation of sets of states. Hence, trade-offs between cost and precision can be made by plugging in different abstract domains. This is of particular importance in the case of hardware verification, where one of the major obstacle to the integration of automatic tools in the design flow is the state-explosion problem they face. We instantiate our analysis with a domain that consists in a collection of vectors of constants and whose size is linear in the size of the unit under verification. Among other things, our analysis allows us to assert safety properties.