As high performance parallel computing architectures make their way into systems with tight size, weight, power, and energy budgets (e.g., portable computing and communications, autonomous vehicles, and space-borne computing), compact and efficient computing and communication mechanisms will be required. To provide such a communication mechanism, the Portable Image Computing Architectures (PICA) group at Georgia Tech is designing the High-Performance Efficient Router (HiPER), a multidimensional router with high-throughput serial channels (1-2 Gbps). Providing high performance for size, weight, power, and energy constrained systems requires careful attention to routing, switching, and error control mechanisms, and the HiPER Prototype (HiPER-P) is a proof-of-concept vehicle that will validate efficient implementations of these mechanisms. The HiPER-P combines mad postman (bit- pipelined) switching with dimension-order routing, producing a router with a very low-latency routing function. To maintain robust communication as link speeds increase and link power budgets decrease, the HiPER-P provides flit-level hop-by-hop retransmission of erroneous flits. This error control mechanism provides built-in error control at the network level. The design of the HiPER-P is presented in this paper as well as results of performance simulations which characterize mad postman switching combined with flit-level error control.