This paper presents an optimized 64-bit parallel adder. Sparse-tree architecture enables low carry-merge fan-outs and inter-stage
wiring complexity. Single-rail and semi-dynamic circuit improves operation speed. Simulation results show that the proposed
adder can operate at 485ps with power of 25.6mW in 0.18
μm CMOS process. It achieves the goal of higher speed and lower power.
Keywords parallel prefix adder - semi-dynamic - sparse-tree
Supported by the National Natural Science Foundation of China under Grant Nos. 60273069, 60376018, 90207011, the National
High Technology Development 863 Program of China under Grant No. 2002AA110020, and the Advanced Research Foundation of NUDT
under Grant No. JC03-06-007.