A 155 Mbps Triple-DES Network Encryptor
Herbert Leitold6, Wolfgang Mayerwieser6, Udo Payer6, Karl Christian Posch6, Reinhard Posch6 and Johannes Wolkerstorfer6 
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Institute for Applied Information Processing and Communications, Graz University of Technology, Inffeldgasse 16a, A-8010 Graz, Austria |
Abstract
The presented Triple-DES encryptor is a single-chip solution to encrypt network communication. It is optimized for throughput
and fast switching between virtual connections like found in ATM networks. A broad range of optimization techniques were applied
to reach encryption rates above 155 Mbps even for Triple-DES encryption in outer CBC mode. A high-speed logic style and full-custom
design methodology made first-time working silicon on a standard 0.6μm CMOS process possible. Correct functionality of the
prototype was verified up to a clock rate of 275 MHz.
Keywords Network security - encryption - DES algorithm - Triple-DES - cipher block chaining - pipelining - true single-phase logic - full-custom design
The work described origins from the European Comission funded Project Secure Communications in ATM Networks (SCAN) established under contract AC0330 in the Advanced Communications Technologies and Services (ACTS)Program.
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