A new system for research on hardware evolution of analog VLSI circuits is proposed. The heart of the system is a CMOS chip providing an array of 16 × 16 transistors programmable in their channel dimensions as well as in their connectivity. A genetic algorithm is executed on a PC connected to one or more programmable transistor arrays (PTA). Individuals are represented by a given configuration of the PTA. The fitness of each individual is determined by measuring the output of the PTA chip, yielding a high test rate per indiviuum. The feasibility of the chosen approach is discussed as well as some of the advantages and limitations inherent to the system by means of simulation results.