Front matter
275-288
The First Quartz Electronic Watch
Christian Piguet
359-372
An Improved Power Macro-Model for Arithmetic Datapath Components
D. Helms, E. Schmidt, A. Schulz, A. Stammermann and W. Nebel
541-552
Performance Comparison of VLSI Adders Using Logical Effort
Hoang Q. Dao and Vojin G. Oklobdzija
271-282
MDSP: A High-Performance Low-Power DSP Architecture
F. Pessolano, J. Kessels and A. Peeters
165-180
Impact of Technology in Power-Grid-Induced Noise
Juan-Antonio Carballo and Sani R. Nassif
445-456
Exploiting Metal Layer Characteristics for Low-Power Routing
Armin Windschiegl, Paul Zuber and Walter Stechele
51-56
Crosstalk Measurement Technique for CMOS ICs
F. Picot, P. Coll and D. Auvergne
263-290
Instrumentation Set-up for Instruction Level Power Modeling
S. Nikolaidis, N. Kavvadias, P. Neofotistos, K. Kosmatopoulos and T. Laopoulos, et al.
15-37
Low-Power Asynchronous A/D Conversion
Emmanuel Allier, Laurent Fesquet, Marc Renaudin and Gilles Sicard
1-24
Optimal Two-Level Delay — Insensitive Implementation of Logic Functions
Igor Lemberski and Mark Josephs
307-326
Resonant Multistage Charging of Dominant Capacitances
Christoph Saas and Josef A. Nossek
147-164
A New Methodology to Design Low-Power Asynchronous Circuits
Oscar Garnica, Juan Lanchares and Román Hermida
225-238
Designing Carry Look-Ahead Adders with an Adiabatic Logic Standard-Cell Library
Antonio Blotti, Maurizio Castellucci and Roberto Saletti
211-218
Clocking and Clocked Storage Elements in Multi-GHz Environment
Vojin G. Oklobdzija
25-40
Dual Supply Voltage Scaling in a Conventional Power-Driven Logic Synthesis Environment
Torsten Mahnke, Walter Stechele and Wolfgang Hoeld
239-252
Transistor Level Synthesis Dedicated to Fast I.P. Prototyping
A. Landrault, L. Pellier, A. Richard, C. Jay and M. Robert, et al.
253-274
Robust SAT-Based Search Algorithm for Leakage Power Reduction
Fadi A. Aloul, Soha Hassoun, Karem A. Sakallah and David Blaauw
389-412
PA-ZSA (Power-Aware Zero-Slack Algorithm): A Graph-Based Timing Analysis for Ultra-Low Power CMOS VLSI
Kyu-won Choi and Abhijit Chatterjee
117-122
A New Methodology for Efficient Synchronization of RNS-Based VLSI Systems
Daniel González, Antonio García, Graham A. Jullien, Javier Ramírez and Luis Parrilla, et al.
327-344
Clock Distribution Network Optimization under Self-Heating and Timing Constraints
M. R. Casu, M. Graziano, G. Masera, G. Piccinini and M. M. Prono, et al.
505-520
A Technique to Generate CMOS VLSI Flip-Flops Based on Differential Latches
Raúl Jiménez, Pilar Parra, Pedro Sanmartín and Antonio Acosta
71-88
A Compact Charge-Based Propagation Delay Model for Submicronic CMOS Buffers
José Luis Rossello and Jaume Segura
39-49
Output Waveform Evaluation of Basic Pass Transistor Structure
S. Nikolaidis, H. Pournara and A. Chatzigeorgiou
413-428
An Approach to Energy Consumption Modeling in RC Ladder Circuits
M. Alioto, G. Palumbo and M. Poli
7-13
Structure Independent Representation of Output Transition Time for CMOS Library
P. Maurine, N. Azemard and D. Auvergne
187-195
A Low Energy Clustered Instruction Memory Hierarchy for Long Instruction Word Processors
Murali Jayapala, Francisco Barat, Pieter Op de Beeck, Francky Catthoor and Geert Deconinck, et al.
229-245
Design and Realization of a Low Power Register File Using Energy Model
Zhao Xue-mei and Ye Yi-zheng
289-306
Register File Energy Reduction by Operand Data Reuse
Hiroshi Takamura, Koji Inoue and Vasily G. Moshnyaga
219-227
Energy-Efficient Design of the Reorder Buffer
Dmitry Ponomarev, Gurhan Kucuk and Kanad Ghose
99-112
Trends in Ultralow-Voltage RAM Technology
Kiyoo Itoh
457-472
Offine Data Profiling Techniques to Enhance Memory Compression in Embedded Systems
Luca Benini, Alberto Macii and Enrico Macii
283-370
Performance and Power Comparative Study of Discrete Wavelet Transform on Programmable Processors
N. D. Zervas, G. Pagkless, M. Dasigenis and D. Soudris
237-261
Power Consumption Estimation of a C Program for Data-Intensive Applications
Eric Senn, Nathalie Julien, Johann Laurent and Eric Martin
181-196
A Low Overhead Auto-Optimizing Bus Encoding Scheme for Low Power Data Transmission
Claudia Kretzschmar, Robert Siegmund and Dietmar Müller
353-362
Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level
C. Baena, J. Juan-Chico, M. J. Bellido, P. Ruiz de Clavijo and C. J. Jiménez, et al.
173-186
Low-Power FSMs in FPGA: Encoding Alternatives
G. Sutter, E. Todorovich, S. Lopez-Buedo and E. Boemo
197-209
Synthetic Generation of Events for Address-Event-Representation Communications
Alejandro Linares-Barranco, Gabriel Jiménez, Antón Civit and Bernabé Linares-Barranco
123-137
Reducing Energy Consumption via Low-Cost Value Prediction
Toshinori Sato and Itsujiro Arita
155-171
Dynamic Voltage Scheduling for Real Time Asynchronous Systems
Mohammed Es Salhiene, Laurent Fesquet and Marc Renaudin
315-339
Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level
Paulino Ruiz-de-Clavijo, Jorge Juan, Manuel J. Bellido, Alejandro Millán and David Guerrero
57-70
Power Efficient Vector Quantization Design Using Pixel Truncation
Kostas Masselos, Panagiotis Merakos and Costas E. Goutis
235-236
Minimizing Spurious Switching Activities in CMOS Circuits
Artur Wróblewski, Florian Auernhammer and Josef A. Nossek
291-314
Modeling Propagation Delay of MUX, XOR, and D-Latch Source-Coupled Logic Gates
M. Alioto and G. Palumbo
503-504
Operating Region Modelling and Timing Analysis of CMOS Gates Driving Transmission Lines
Gregorio Cappuccino and Giuseppe Cocorullo
448-457
Selective Clock-Gating for Low Power/Low Noise Synchronous Counters
Pilar Parra, Antonio Acosta and Manuel Valencia
247-269
Probabilistic Power Estimation for Digital Signal Processing Architectures
Achim Freimann
1-6
Modeling of Propagation Delay of a First Order Circuit with a Ramp Input
Rosario Mita and Gaetano Palumbo
57-74
Characterization of Normal Propagation Delay for Delay Degradation Model (DDM)
Alejandro Millán, Jorge Juan, Manuel J. Bellido, Paulino Ruiz-de-Clavijo and David Guerrero
139-153
Automated Design Methodology for CMOS Analog Circuit Blocks in Complex Systems
Razvan Ionita, Andrei Vladimirescu and Paul Jespers
Back matter