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Book Chapter
Area-Aware Pipeline Gating for Embedded Processors
Book Series
Lecture Notes in Computer Science
Publisher
Springer Berlin / Heidelberg
ISSN
0302-9743 (Print) 1611-3349 (Online)
Volume
Volume 3728/2005
Book
Integrated Circuit and System Design
DOI
10.1007/11556930
Copyright
2005
ISBN
978-3-540-29013-1
Category
Poster Session 2: Digital Circuits
DOI
10.1007/11556930_61
Pages
601-608
Subject Collection
Computer Science
SpringerLink Date
Tuesday, August 23, 2005
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Poster Session 2: Digital Circuits
Area-Aware Pipeline Gating for Embedded Processors
Babak Salamat
1
and Amirali Baniasadi
1
(1)
Electrical and Computer Engineering, University of Victoria,
Abstract
Modern embedded processors use small and simple branch predictors to improve performance. Using complex and accurate branch predictors, while desirable, is not possible as such predictors impose high power and area overhead which is not affordable in an embedded processor. As a result, for some applications, misprediction rate can be high. Such mispredictions result in energy wasted down the mispredicted path. We introduce area-aware and low-complexity pipeline gating mechanisms to reduce energy lost to possible branch mispredictions in embedded processors. We show that by using a simple gating mechanism which comes with 33-bit area overhead, on average, we can reduce the number of executed instructions by 17% (max: 30%) while paying a negligible performance cost (average 1.1%).
Babak
Salamat
Email:
salamat@ece.uvic.ca
Amirali
Baniasadi
Email:
amirali@ece.uvic.ca
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