IP lookup is still considered a hard and challenging problem in routers. In high speeds, around 100Gbps, and with current growth rate of lookup tables, it sounds IP lookup can be a bottleneck. Complexity of the problem stems from the fact that routers must find the longest matching prefix with a packet destination address in the lookup table in order to forward the packet. Basically, this process is slow. We are currently developing a hardware-based scheme, which can perform IP lookup in a time proportional to access time to the external memory. The method implements DMP-tree, Dynamic M-way Prefix tree, which is a superset of B-tree and initially devised for prefix matching. Implemented in a FPGA, the scheme can forward around 100 million packets per second and regarding the average packet size can support IP lookup for over 100Gbps line speed. Our technique scales well to the next generation IP addressing, IPv6.