Over the past few years Ultra Wide Band (UWB) technology has taken the realms of communications circuit design to new levels. This paper demonstrates the design and simulation of a very high speed Flash Analog to Digital Converter (ADC) for UWB applications. The ADC was implemented in 90 nanometre (nm) CMOS design process. The converter works at an optimal sampling rate of 4.1 Gig-Samples per second (Gsps) for an 800 MHz input bandwidth corresponding to a 1V full scale reference. The converter has moderate linearity error tolerance of about ± 1 LSB (62.5 mV) without use of any averaging techniques. The ADC works on a 1V supply and has an overall power consumption of 114 mW.