A Scalable Architecture for Montgomery Nultiplication
Alexandre F. Tenca6 
and Çetin K. Koç6
| (6) |
Electrical & Computer Engineering, Oregon State University, Corvallis, Oregon, 97331 |
Abstract
This paper describes the methodology and design of a scalable Montgomery multiplication module. There is no limitation on
the maximum number of bits manipulated by the multiplier, and the selection of the word-size is made according to the available
area and/or desired performance. We describe the general view of the new architecture, analyze hardware organization for its
parallel computation, and discuss design tradeoffs which are useful to identify the best hardware configuration.
Acknowledgements This research is supported in part by Secured Information Technology, Inc. The authors would like to thank Erkay Savaş (Oregon
State University) for his comments on the algorithm definition.
Readers should note that Oregon State University has filed or will file a patent application containing this work to the US
Patent and Trademark Office.
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