Front matter
1-12
On Fireflies, Cellular Systems, and Evolware
Christof Teuscher and Mathieu S. Capcarrere
13-23
A Comparison of Different Circuit Representations for Evolutionary Analog Circuit Design
Lyudmilla Zinchenko, Heinz Mühlenbein, Victor Kureichik and Thilo Mahnig
24-34
Fault Tolerance via Endocrinologic Based Communication for Multiprocessor Systems
Andrew J. Greensted and Andy M. Tyrrell
35-46
Using Negative Correlation to Evolve Fault-Tolerant Circuits
Thorsten Schnier and Xin Yao
47-56
A Genetic Representation for Evolutionary Fault Recovery in Virtex FPGAs
Jason Lohn, Greg Larchev and Ronald DeMara
57-68
Biologically Inspired Evolutionary Development
Sanjeev Kumar and Peter J. Bentley
69-80
Building Knowledge into Developmental Rules for Circuit Design
Gunnar Tufte and Pauline C. Haddow
81-92
Evolving Fractal Proteins
Peter J. Bentley
93-104
A Developmental Method for Growing Graphs and Circuits
Julian F. Miller and Peter Thomson
105-116
Developmental Models for Emergent Computation
Keith L. Downing
117-128
Developmental Effects on Tuneable Fitness Landscapes
Piet van Remortel, Johan Ceuppens, Anne Defaweux, Tom Lenaerts and Bernard Manderick
129-140
POEtic Tissue: An Integrated Architecture for Bio-inspired Hardware
Andy M. Tyrrell, Eduardo Sanchez, Dario Floreano, Gianluca Tempesti and Daniel Mange, et al.
141-152
Ontogenetic Development and Fault Tolerance in the POEtic Tissue
Gianluca Tempesti, Daniel Roggen, Eduardo Sanchez, Yann Thoma and Richard Canham, et al.
153-164
A Morphogenetic Evolutionary System: Phylogenesis of the POEtic Circuit
Daniel Roggen, Dario Floreano and Claudio Mattiussi
165-173
Spiking Neural Networks for Reconfigurable POEtic Tissue
Jan Eriksson, Oriol Torres, Andrew Mitchell, Gayle Tucker and Ken Lindsay, et al.
174-185
A Learning, Multi-layered, Hardware Artificial Immune System Implemented upon an Embryonic Array
Richard Canham and Andy M. Tyrrell
186-197
Virtual Reconfigurable Circuits for Real-World Applications of Evolvable Hardware
Lukáš Sekanina
198-207
Gene Finding Using Evolvable Reasoning Hardware
Moritoshi Yasunaga, Ikuo Yoshihara and Jung H. Kim
208-217
Evolvable Fuzzy System for ATM Cell Scheduling
J. H. Li and M. H. Lim
218-227
Synthesis of Boolean Functions Using Information Theory
Arturo Hernández Aguirre, Edgar C. González Equihua and Carlos A. Coello Coello
228-237
Evolving Multiplier Circuits by Training Set and Training Vector Partitioning
Jim Torresen
238-248
Evolution of Self-diagnosing Hardware
Miguel Garvie and Adrian Thompson
249-261
Routing of Embryonic Arrays Using Genetic Algorithms
Cesar Ortega-Sanchez, Jose Torres-Jimenez and Jorge Morales-Cruz
262-273
Exploiting Auto-adaptive μGP for Highly Effective Test Programs Generation
F. Corno, F. Cumani and G. Squillero
274-285
Speeding up Hardware Evolution: A Coprocessor for Evolutionary Algorithms
Tillmann Schmitz, Steffen Hohmann, Karlheinz Meier, Johannes Schemmel and Felix Schürmann
286-295
Automatic Evolution of Signal Separators Using Reconfigurable Hardware
Ricardo S. Zebulum, Adrian Stoica, Didier Keymeulen, M. I. Ferguson and Vu Duong, et al.
296-307
Distributed Control in Self-reconfigurable Robots
Henrik Hautop Lund, Rasmus Lock Larsen and Esben Hallundbæk Østergaard
308-319
Co-evolving Complex Robot Behavior
Esben Hallundbæk Óstergaard and Henrik Hautop Lund
320-331
Evolving Reinforcement Learning-Like Abilities for Robots
Jesper Blynel
332-343
Evolving Image Processing Operations for an Evolvable Hardware Environment
Stephen L. Smith, David P. Crouch and Andy M. Tyrrell
344-354
Hardware Implementation of a Genetic Controller and Effects of Training on Evolution
M. A. Hannan Bin Azhar and K. R. Dimond
355-364
Real World Hardware Evolution: A Mobile Platform for Sensor Evolution
Robert Goldsmith
365-376
Real-Time Reconfigurable Linear Threshold Elements and Some Applications to Neural Hardware
Snorre Aunet and Morten Hartmann
377-386
Simulation of a Neural Node Using SET Technology
Rudie van de Haar and Jaap Hoekstra
387-397
General Purpose Processor Architecture for Modeling Stochastic Biological Neuronal Assemblies
N. Venkateswaran and C. Chandramouli
398-409
Use of Particle Swarm Optimization to Design Combinational Logic Circuits
Carlos A. Coello Coello, Erika Hernández Luna and Arturo Hernández Aguirre
410-421
A Note on Designing Logical Circuits Using SAT
Giovani Gomez Estrada
422-433
Using Genetic Programming to Generate Protocol Adaptors for Interprocess Communication
Werner Van Belle, Tom Mens and Theo D’Hondt
434-445
Using Genetic Programming and High Level Synthesis to Design Optimized Datapath
Sérgio G. Araújo, A. Mesquita and Aloysio C. P. Pedroza
446-456
The Effect of the Bulge Loop upon the Hybridization Process in DNA Computing
Fumiaki Tanaka, Atsushi Kameda, Masahito Yamamoto and Azuma Ohuchi
457-465
Quantum versus Evolutionary Systems. Total versus Sampled Search
Hugo de Garis, Amit Gaur and Ravichandra Sriram
Back matter