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Koen Bertels, Nikitas Dimopoulos, Cristina Silvano and Stephan Wong
Front matter
1
What Else Is Broken? Can We Fix It?
2-11
Programmable and Scalable Architecture for Graphics Processing Units
12-23
The Abstract Streaming Machine: Compile-Time Performance Modelling of Stream Programs on Heterogeneous Multiprocessors
24-35
CABAC Accelerator Architectures for Video Compression in Future Multimedia: A Survey
36-47
Programmable Accelerators for Reconfigurable Video Decoder
48-57
Scenario Based Mapping of Dynamic Applications on MPSoC: A 3D Graphics Case Study
58-67
Multiple Description Scalable Coding for Video Transmission over Unreliable Networks
68-77
Evaluation of Different Multithreaded and Multicore Processor Configurations for SoPC
78-87
Implementing Fine/Medium Grained TLP Support in a Many-Core Architecture
88-97
Implementation of W-CDMA Cell Search on a FPGA Based Multi-Processor System-on-Chip with Power Management
98-107
A Multiprocessor Architecture with an Omega Network for the Massively Parallel Model GCA
108-117
Towards Automated FSMD Partitioning for Low Power Using Simulated Annealing
118-127
Radix-4 Recoded Multiplier on Quantum-Dot Cellular Automata
128-138
Prediction in Dynamic SDRAM Controller Policies
139-148
Inversion/Non-inversion Implementation for an 11,424 Gate-Count Dynamic Optically Reconfigurable Gate Array VLSI
149-160
Visualization of Computer Architecture Simulation Data for System-Level Design Space Exploration
161-170
Modeling Scalable SIMD DSPs in LISA
171-180
NoGAP: A Micro Architecture Construction Framework
181-192
A Comparison of NoTA and GENESYS
193
Introduction to Instruction-Set Customization
194-203
Constraint-Driven Identification of Application Specific Instructions in the DURASE System
204-214
A Generic Design Flow for Application Specific Processor Customization through Instruction-Set Extensions (ISEs)
215-225
Runtime Adaptive Extensible Embedded Processors — A Survey
226
Introduction to the Future of Reconfigurable Computing and Processor Architectures
227-236
An Embrace-and-Extend Approach to Managing the Complexity of Future Heterogeneous Systems
237-246
Applying the Stream-Based Computing Model to Design Hardware Accelerators: A Case Study
247-254
Reconfigurable Multicore Server Processors for Low Power Operation
255-262
Reconfigurable Computing in the New Age of Parallelism
263-274
Reconfigurable Multithreading Architectures: A Survey
275-276
Introduction to Mastering Cell BE and GPU Execution Platforms
277-288
Efficient Mapping of Multiresolution Image Filtering Algorithms on Graphics Processors
289-297
Implementing Blocked Sparse Matrix-Vector Multiplication on NVIDIA GPUs
298-307
Experiences with Cell-BE and GPU for Tomography
308-317
Realizing FIFO Communication When Mapping Kahn Process Networks onto the Cell
318-328
Exploiting Locality on the Cell/B.E. through Bypassing
329-339
Exploiting the Cell/BE Architecture with the StarPU Unified Runtime System
Back matter
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