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Abstract

A multilayer conductor-insulator technology suitable for semiconductor memories has been developed utilizing materials and fabrication techniques compatible with high density LSI structures. Interactions between failure modes, structure design, and process design are presented.
Both aluminum-silicon contact windows and interlayer (via) conductor windows must be sloped with appropirate contours to avoid discontinuous metal coverage. The processing involves compatible compositions of multicomponent oxides and a via delineation etch which permits extensive oxide removal without a simultaneous aluminum attack.
Intra- and inter- connects are formed from electron beamed aluminum films deposited in a planetary system onto substrates at 300°C (room temperature for first level conductors in a CMOS structure). Desirable film properties include relatively large grain size, low hillock density and complete step coverage.
Insulator layers are formed by the chemical vapor deposition of SiO2 as a product of the oxidation of silane gas. The dielectric protrusions over aluminum hillocks are exaggerated. In addition, bulbous glass is formed over the edges of aluminum stripes unless these intraconnects have a trapezoidal cross-section. This configuration is formed with an H3PO4-HNO3-HAc aluminum delineation etch. Glass-enhanced aluminum hillocks can cause both intraconnect opens and interlayer shorts during conductor and via etching unless compensating topographic/photoengraving design rules are observed.

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