Fine grained reconfigurable architectures, like Xilinx field programmable gate arrays (FPGAs) provide a high flexibility through runtime re-programming, called dynamic and partial reconfiguration. This feature allows for runtime adaptation of the system architecture and behavior configured on the FPGA. The exploitation of this feature enables to load video image processing algorithms on-demand in order to adapt the configuration in correspondence to the changing requirements of the application depending on the image content. For high resolution sensor images, this novel computing paradigm can provide a huge benefit in power reduction and performance gain for actual and future embedded electronic systems. This paper presents a two dimensional system approach exploiting dynamic and partial reconfiguration in order to adapt the system architecture to the actual requirements of image processing applications. The methodology of runtime reconfiguration can be exploited beneficially for highly adaptive multiprocessor systems. Such systems, different from the traditional static approach for multi- and many-core architectures have the advantage, for providing computational performance directly linked to the requirements of the application. The architecture presented in this paper allows for adapting the processing elements as well as the communication infrastructure which is a novel 2D switch-based Network-on-Chip. The presented approach follows and extends the actual trend in computer science of using many- and multi-core processors for bridging the gap between required computation performance for future application in the field of image processing.