As the size of CMOS devices is approaching the atomic level, the increasing intrinsic device variability is leading to higher failure rates in conventional CMOS designs. In this paper, two approaches are proposed for evolving unconventional variability-tolerent CMOS designs: one uses a simple Genetic Algorithm, whilst the other uses Cartesian Genetic Programming. Both approaches successfully evolve unconventional designs for logic gates, whilst an inverter design also shows signs of variability-tolerance.