In this paper a system for the design of massively parallel processor arrays is presented. We describe new methods for the consideration of hardware constraints and of performance criteria in the design process. In particular, we focus on the determination of a full size array for the original algorithm which we want to implement in silicon. The arising optimization problems can be solved using integer linear programming. Furthermore, we describe methods for adapting the full size arrays to hardware constraints of a target architecture which is embedded in a peripheral system.