A low-power, multi-stage delta-sigma modulator with comparator-based switched-capacitor (CBSC) gain stages is presented. The presented design eliminates the need for operational amplifiers and replaces them by comparators with current sources at their outputs to alleviate the effects of continued technology scaling on analog and mixed-signal circuits. The proposed technique significantly reduces power consumption and can be applied to switched-capacitor delta-sigma modulators of arbitrary order. Based on the proposed methodology, a 2-1 cascade, single-bit, pseudo-differential switched-capacitor delta-sigma modulator is developed and achieves a SNDR of 76.8 dB with an oversampling ratio of 64 at a clock frequency of 8 MHz.