Evolutionary algorithms are useful optimization tools but are very time consuming to run. We present a self-contained FPGA-based implementation of a spatially-structured evolutionary algorithm that provides significant speedup over conventional serial processing in three ways: (a) efficient hardware-pipelined fitness evaluation of individuals, (b) evaluation of an entire population of individuals in parallel, and (c) elimination of slow off-chip communication. We demonstrate using the system to solve a non-trivial signal reconstruction problem using a non-linear digital filter on a Xilinx Virtex FPGA, and find a speedup factor of over 1000 compared to a C implementation of the same system. The general principles behind the system are very scalable, and as FPGAs become even larger in the future, similar systems will provide extremely large speedups over serial processing.