SpringerLink - Journal Article

Power Dissipation of the Network-on-Chip in Multi-Processor System-on-Chip Dedicated for Video Coding Applications

Dragomir Milojevic¹, Luc Montperrus² and Diederik Verkest³

(1)	Faculty of Applied Sciences; Bio, Electro and Mechanical Systems Department, Université Libre de Bruxelles - ULB, ULB CP-165/56, Av. F. Roosevelt 50, 1050 Bruxelles, Belgium

(2)	Arteris S.A., 6 Parc Ariane Immeuble Mercure, Boulevard des Chenes, 78284 Guyancourt Cedex, France

(3)	Interuniversity Microelectronics Centre - IMEC, Kapeldreef 75, 3001 Leuven, Belgium

Received: 29 May 2007 Revised: 8 June 2008 Accepted: 23 June 2008 Published online: 29 July 2008

Abstract In the near future, small electronic hand-held devices will be equipped with digital cameras capable of acquiring high resolution images (HDTV) at real-time rates, resulting in video streams of dozens of megabytes per second. The real-time video decoding and especially encoding of such streams with AVC/ H.264 or SVC standards require a huge amount of computing power that, in the case of a hand-held device, has to be delivered under the constraint of low power dissipation. In this paper we present a Multi-Processor System-on-Chip dedicated for high performance, low-power video coding applications using Network-on-Chip (NoC) as communication infrastructure. Extensive experiments have established the power dissipation models of individual NoC components, i.e. network interfaces, routers and wires. Based on these models and the NoC topology, we build the power model of the complete NoC. For three different implementation scenarios of the AVC/H.264 simple profile encoder we derive the power dissipation of the NoC for image resolutions up to HDTV at rate of 30 frames per second. The results obtained show that for the same application mapping scenario (worst case), moving from CIF to HDTV resolution will result in a 35% increase of the total power dissipation. Finally, for HDTV resolution, the difference in power dissipation between the worst (21 mW) and the best case application mapping scenario is 26%.

Keywords Multi-processor systems-on-chip (MPSoC) - Networks-on-chip (NoC) - Real-time video encoding, decoding - AVC/H.264 - Low-power VLSI implementation

This research has been carried out in the context of IMEC’s multimode multimedia program which is partially sponsored by Samsung and Freescale. The authors would also like to thank Xavier Leloup, Gilles Baillieu and Jean-Yves Mignolet for their invaluable help.

Dragomir Milojevic (Corresponding author)
Email: Dragomir.Milojevic@ulb.ac.be

Luc Montperrus
Email: Luc.Montperrus@arteris.com

Diederik Verkest
Email: Diederik.Verkest@imec.be

Dragomir Milojevic received his Master of Science in Electrical and Mechanical Engineering and his Ph.D. in Electrical Engineering from Université Libre de Bruxelles (ULB), Bruxelles, Belgium in 1994 and 2004 respectively. Since 1995 he has been with Information and Decisions Systems Laboratory, ULB as assistant professor. Since 2004 he joined Interuniversity Microelectronics Centre (IMEC), Leuven, Belgium as invited researcher. He currently holds the position of associate professor at Faculty of Applied Sciences at ULB in Embedded Electronics research unit of Bio-, Electro- And Mechanical Systems department. His research work is mainly focused on design, optimisation and implementation of efficient hardware architectures/algorithms for image and video processing and system level design tools. He is a member of the programme and/or organisation committees of international conferences DASIP and SAMOS.

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Luc Montperrus graduated from the Ecole Centrale de Paris in 1981 with a degree in bio-engineering. He then obtained a specialized degree in electronics from Ecole Supérieure d’Electricité (Supélec) in 1984, followed by a PhD in Microelectronics (highly parallel operator architectures) from the Université de Paris XI. In 1985 he joined MHS, a Matra group company, where he initially designed operators and chips for video applications, then later integrated the Sparc microcontroller project team. In 1997 he was hired by Tsqware, a MHS spin off, where he specialized in the development of multi-processor telecommunication chips. He currently works as a chip physical implementation and industrial property expert for Arteris, a leading provider of network-on-chip technology.

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Diederik Verkest received the Master and Ph.D. degree in Applied Sciences from the Katholieke Universiteit Leuven (Belgium) in 1987 and 1994, respectively. He has been working in the VLSI design methodology group of the IMEC laboratory (Leuven, Belgium) on several topics related to formal methods, system design, hardware/software co-design, re-configurable systems, and multi-processor systems. He is currently in charge of the research at IMEC on design technology for nomadic embedded systems. Diederik Verkest is Professor at the University of Brussels (VUB) and at the University of Leuven (KU-Leuven). He is member of IEEE and a Golden Core Member of the IEEE Computer Society. He published and presented over 150 articles in International Journals and at International Conferences. Over the past years he was a member of the programme and/or organisation committees of several major international conferences such as ISSS, CODES, FPL, DATE, and DAC. He was the General Chair of the Design, Automation and Test in Europe Conference, DATE’03, and of ASAP’08.

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Power Dissipation of the Network-on-Chip in Multi-Processor System-on-Chip Dedicated for Video Coding Applications

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