Generally, reconfigurable logic devices have been classified as fine-grained or coarse-grained devices depending on the input size of their logic cells. These architectures have conflicting characteristics, which limits their application domain for an efficient implementation. In order to solve this constraint, we propose a variable grain logic cell (VGLC) architecture that exhibits the characteristics of both fine-grained and coarse-grained cells. In this study, we investigate a VGLC structure and its mapping technique. We evaluate the capability of VGLC with respect to its critical path delay, implementation area, and configuration data bits; we propose a maximum improvement of 49.7%, 54.6%, and 48.5% in these parameters, respectively.