Targeting at the high expense and inflexibility to realize VMEbus bridge controller by professional Integrated Circuit (IC),
this paper presents a scheme of adopting CPLD/FPGA (Complicated Programmable Logic Device/Field Programmable Gate Array) to
design bridge controller between VMEbus and local bus. SHARC DSP (Digital Signal Processor) bus is an example. It has functions
of nearly entire master/slave interface of VMEbus, and can act as DMA (Direct Memory Access) controller and perform block
transfer in DMA or master processor initiative way without length limit. External circuit of the design is very simple. In
comparison with special ICs, it has high performance to price ratio and can be easily applied to local buses of other processors
with quite a little modification.
Key words VMEbus - Bridge controller - Complicated Programmable Logic Device(CPLD) - Master - Slave - SHARC bus
Communication author: Wang Min, born in 1977, male, Ph.D. student. Key Lab for Radar Signal Processing of Xidian University,
Xi’an 710071, China.