Front matter
1
What Is beyond the RTL Horizon for Microprocessor and System Design?
Wolfgang Roesner
2
The Charme of Abstract Entities
Fabio Somenzi
3
The PSL/Sugar Specification Language A Language for all Seasons
Daniel Geist
4-18
Finding Regularity: Describing and Analysing Circuits That Are Not Quite Regular
Mary Sheeran
19-34
Predicate Abstraction with Minimum Predicates
Sagar Chaki, Edmund Clarke, Alex Groce and Ofer Strichman
35-50
Efficient Symbolic Model Checking of Software Using Partial Disjunctive Partitioning
Sharon Barner and Ishai Rabinovitz
51-65
Instantiating Uninterpreted Functional Units and Memory System: Functional Verification of the VAMP
Sven Beyer, Chris Jacobi, Daniel Kröning, Dirk Leinenbach and Wolfgang J. Paul
66-80
A Hazards-Based Correctness Statement for Pipelined Circuits
Mark D. Aagaard
81-95
Analyzing the Intel Itanium Memory Ordering Rules Using Logic Programming and SAT
Yue Yang, Ganesh Gopalakrishnan, Gary Lindstrom and Konrad Slind
96-110
On Complementing Nondeterministic Büchi Automata
Sankar Gurumurthy, Orna Kupferman, Fabio Somenzi and Moshe Y. Vardi
111-125
Coverage Metrics for Formal Verification
Hana Chockler, Orna Kupferman and Moshe Y. Vardi
126-140
“More Deterministic” vs. “Smaller” Büchi Automata for Efficient LTL Model Checking
Roberto Sebastiani and Stefano Tonetta
141-149
An Optimized Symbolic Bounded Model Checking Engine
Rachel Tzoref, Mark Matusevich, Eli Berger and Ilan Beer
150-157
Constrained Symbolic Simulation with Mathematica and ACL2
Ghiath Al Sammane, Diana Toma, Julien Schmaltz, Pierre Ostier and Dominique Borrione
158-163
Semi-formal Verification of Memory Systems by Symbolic Simulation
Husam Abu-Haimed, Sergey Berezin and David L. Dill
164-169
CTL May Be Ambiguous When Model Checking Moore Machines
Cédric Roux and Emmanuelle Encrenaz
170-184
Reasoning about GSTE Assertion Graphs
Alan J. Hu, Jeremy Casas and Jin Yang
185-199
Towards Diagrammability and Efficiency in Event Sequence Languages
Kathi Fisler
200-215
Executing the Formal Semantics of the Accellera Property Specification Language by Mechanised Theorem Proving
Mike Gordon, Joe Hurd and Konrad Slind
216-230
On Combining Symmetry Reduction and Symbolic Representation for Efficient Model Checking
E. Allen Emerson and Thomas Wahl
231-246
On the Correctness of an Intrusion-Tolerant Group Communication Protocol
Mohamed Layouni, Jozef Hooman and Sofiène Tahar
247-262
Exact and Efficient Verification of Parameterized Cache Coherence Protocols
E. Allen Emerson and Vineet Kahlon
263-269
Design and Implementation of an Abstract Interpreter for VHDL
Charles Hymans
270-276
A Programming Language Based Analysis of Operand Forwarding
Lennart Beringer
277-282
Integrating RAM and Disk Based Verification within the Murϕ Verifier
Giuseppe Della Penna, Benedetto Intrigila, Igor Melatti, Enrico Tronci and Marisa Venturini Zilli
283-288
Design and Verification of CoreConnectTM IP Using Esterel
Satnam Singh
289-303
Inductive Assertions and Operational Semantics
J Strother Moore
304-318
A Compositional Theory of Refinement for Branching Time
Panagiotis Manolios
319-333
Linear and Nonlinear Arithmetic in ACL2
Warren A. Hunt, Robert Bellarmine Krug and J. Moore
334-347
Efficient Distributed SAT and SAT-Based Distributed Bounded Model Checking
Malay K Ganai, Aarti Gupta, Zijiang Yang and Pranav Ashar
348-362
Convergence Testing in Term-Level Bounded Model Checking
Randal E. Bryant, Shuvendu K. Lahiri and Sanjit A. Seshia
363-377
The ROBDD Size of Simple CNF Formulas
Michael Langberg, Amir Pnueli and Yoav Rodeh
378-393
Efficient Hybrid Reachability Analysis for Asynchronous Concurrent Systems
Enric Pastor and Marco A. Peña
394-409
Finite Horizon Analysis of Markov Chains with the Murϕ Verifier
Giuseppe Della Penna, Benedetto Intrigila, Igor Melatti, Enrico Tronci and Marisa Venturini Zilli
410-424
Improved Symbolic Verification Using Partitioning Techniques
Subramanian Iyer, Debashis Sahoo, Christian Stangier, Amit Narayan and Jawahar Jain
Back matter