The FPGA has provided us low cost yet extremely powerful reconfigurable hardware, which provides excellent scope for the implementation of parallel algorithms. We propose that despite having this enormous potential at our fingertips, we are somewhat lacking in techniques to properly exploit it. We propose a development strategy commencing with a clear, intuitive and provably correct specification in a functional language such as Haskell. We then take this specification, and, applying a set of formal transformation laws, refine it into a behavioural definition in Handel-C, exposing the implicit parallelism along the way. This definition can then be compiled onto an FPGA.