In this chapter we analyze the Synergistic Processing Elements (SPE) of the Cell Broadband Engine. The 6 identical SPEs (in the PS3, 8 in the general Cell processor) are dual-issue SIMD RISC processors optimized for data-rich operations, running off a 256 KB non-cached local store (LS) memory. The SPE ISA and associated DMA commands are optimized for compute intensive work loads. SPEs communicate to the PPE, MIC and other SPEs using the EIB, which is managed by the Memory Flow Controller in the SPE. VLSI system design of the SPE micro-architecture is also presented as the SPU architecture is radically different from the POWER processor VLSI design (since it needs to make a steeper trade-off between performance and silicon area). Additionally, the SPU is also beginning to be shipped as an independent chip (the Toshiba SPURS engine). The performance of the LS, Register Forwarding Macro, Memory Flow Controller, Multi-source Synchronization Facility, and Channel interface is also discussed, as these are used in the subsequent chapters. The ISA of the SPE is also briefly discussed.