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David Kaeli and Kai Sachs
Front matter
1-16
SPECrate2006: Alternatives Considered, Lessons Learned
17-35
SPECjvm2008 Performance Characterization
36-56
Performance Characterization of Itanium® 2-Based Montecito Processor
57-76
A Tale of Two Processors: Revisiting the RISC-CISC Debate
77-96
Investigating Cache Parameters of x86 Family Processors
97-101
The Next Frontier for Power/Performance Benchmarking: Energy Efficiency of Storage Subsystems
102-120
Thermal Design Space Exploration of 3D Die Stacked Multi-core Processors Using Geospatial-Based Predictive Models
121-137
Generation, Validation and Analysis of SPEC CPU2006 Simulation Points Based on Branch, Memory and TLB Characteristics
138-144
A Note on the Effects of Service Time Distribution in the M/G/1 Queue
Back matter
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