For merged DRAM/logic LSIs with on-chip cache memory, we can exploit the high bandwidth by means of replacing a whole cache line at a time. This approach tends to increase the cache-line size if we attempt to exploit the attainable high bandwidth. A large cache-line size gives a benefit of prefetching effect if programs have rich spatial locality. Otherwise, however, it will bring the following disadvantages due to poor spatial locality:

1.	A number of conflict misses will take place due to frequent evictions.
2.	As a result, a lot of energy will be wasted for on-chip DRAM (main memory) due to a number of main memory accesses.
3.	Activating the wide on-chip bus and the DRAM array will also dissipate a lot of energy.

Employing set-associative caches is a conventional approach to solving the first and second problems, because it can improve cache-hit rates by reducing conflict misses. However, since increasing the cache associativity increases cache-access time and energy, it might worsen the performance/energy efficiency of memory systems. In addition, we still have the third problem.

In order to solve all the problems without any cache-access time and energy overheads, we have proposed the variable line-size cache (VLS cache) architecture for merged DRAM/logic LSIs [3] [4]. The VLS cache exploits the high bandwidth by means of larger cache lines. At the same time, it can alleviate the negative effects of large cache line by partitioning it into multiple small cache lines (sublines). Activating only the DRAM subarrays corresponding to the sublines to be replaced makes a significant energy reduction. In [3] [4], we have discussed only the performance attainable in the VLS cache. This paper evaluates both the performance and energy improvements achieved by the VLS cache architecture.