This paper describes a neural network approach that gives an estimation method for the space complexity of Binary Decision Diagrams (BDDs). A model has been developed to predict the complexity of digital circuits. The formal core of the developed neural network model (NNM) is a unique matrix for the complexity estimation over a set of BDDs derived from Boolean logic expressions with a given number of variables and Sum of Products (SOP) terms. Experimental results show good correlation between the theoretical results and those predicted by the NNM, which will give insights to the complexity of Very Large Scale Integration (VLSI)/Computer Aided Design (CAD) designs. The proposed model is capable of predicting the maximum BDD complexity (MaxBC) and the number of product terms (NPT) in the Boolean function that corresponds to the minimum BDD complexity (MinBC). This model provides an alternative way to predict the complexity of digital VLSI circuits.