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Jürgen Becker, Roger Woods, Peter Athanas and Fearghal Morgan
Front matter
1
FPGA Design Productivity – A Discussion of the State of the Art and a Research Agenda
2
Resiliency in Elemental Computing
3
The Colour of Embedded Computation
4-14
A HyperTransport 3 Physical Layer Interface for FPGAs
15-26
Parametric Design for Reconfigurable Software-Defined Radio
27-38
Hardware/Software FPGA Architecture for Robotics Applications
39-49
Reconfigurable Operator Based Multimedia Embedded Processor
50-61
A Protocol for Secure Remote Updates of FPGA Configurations
62-73
FPGA Analysis Tool: High-Level Flows for Low-Level Design Analysis in Reconfigurable Computing
74-84
An Efficient and Low-Cost Design Methodology to Improve SRAM-Based FPGA Robustness in Space and Avionics Applications
85-96
Timing Driven Placement for Fault Tolerant Circuits Implemented on SRAM-Based FPGAs
97-109
A Novel Local Interconnect Architecture for Variable Grain Logic Cell
110-122
Dynamically Adapted Low Power ASIPs
123-132
Fast Optical Reconfiguration of a Nine-Context DORGA
133-144
Heterogeneous Architecture Exploration: Analysis vs. Parameter Sweep
145-156
On Simplifying Placement and Routing by Extending Coarse-Grained Reconfigurable Arrays with Omega Networks
157-168
A New Datapath Merging Method for Reconfigurable System
169-180
Optimizing the Control Hierarchy of an ECC Coprocessor Design on an FPGA Based SoC Platform
181-192
Fully Pipelined Hardware Implementation of 128-Bit SEED Block Cipher Algorithm
193-203
Improving Throughput of AES-GCM with Pipelined Karatsuba Multipliers on FPGAs
204-215
Compiling Techniques for Coarse Grained Runtime Reconfigurable Architectures
216-230
Online Task Scheduling for the FPGA-Based Partially Reconfigurable Systems
231-242
Word-Length Optimization and Error Analysis of a Multivariate Gaussian Random Number Generator
243-254
FPGA-Based Anomalous Trajectory Detection Using SOFM
255-260
SORU: A Reconfigurable Vector Unit for Adaptable Embedded Systems
261-267
A Parallel Branching Program Machine for Emulation of Sequential Circuits
268-274
Memory Sharing Approach for TMR Softcore Processor
275-280
The Need for Reconfigurable Routers in Networks-on-Chip
281-286
Transparent Dynamic Reconfiguration as a Service of a System-Level Middleware
287-292
Optimizing Memory Access Latencies on a Reconfigurable Multimedia Accelerator: A Case of a Turbo Product Codes Decoder
293-299
Tile-Based Fault Tolerant Approach Using Partial Reconfiguration
300-305
Regular Expression Pattern Matching Supporting Constrained Repetitions
306-311
Accelerating Calculations on the RASC Platform: A Case Study of the Exponential Function
312-317
AES-Galois Counter Mode Encryption/Decryption FPGA Core for Industrial and Residential Gigabit Ethernet Communications
318-323
CCproc: A Custom VLIW Cryptography Co-processor for Symmetric-Key Ciphers
324-329
Object Tracking and Motion Capturing in Hardware-Accelerated Multi-camera System
330-335
Implementation of the AES Algorithm for a Reconfigurable, Bit Serial, Fully Pipelined Architecture
336-341
A Hardware Accelerated Simulation Environment for Spiking Neural Networks
342-348
Survey of Advanced CABAC Accelerator Architectures for Future Multimedia
349-354
Real Time Simulation in Floating Point Precision Using FPGA Computing
355-361
A Hardware Analysis of Twisted Edwards Curves for an Elliptic Curve Cryptosystem
362-367
A Seamless Virtualization Approach for Transparent Dynamical Function Mapping Targeting Heterogeneous and Reconfigurable Systems
368-373
Pipeline Scheduling with Input Port Constraints for an FPGA-Based Biochemical Simulator
374-379
ACCFS – Operating System Integration of Computational Accelerators Using a VFS Approach
380-385
A Multithreaded Framework for Sequential Monte Carlo Methods on CPU/FPGA Platforms
Back matter
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