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Design and Implementation of Rough Rules Generation from Logical Rules on FPGA Board

Design and Implementation of Rough Rules Generation from Logical Rules on FPGA Board

Book SeriesLecture Notes in Computer Science
PublisherSpringer Berlin / Heidelberg
ISSN0302-9743 (Print) 1611-3349 (Online)
VolumeVolume 4585/2007
BookRough Sets and Intelligent Systems Paradigms
DOI10.1007/978-3-540-73451-2
Copyright2007
ISBN978-3-540-73450-5
DOI10.1007/978-3-540-73451-2_62
Pages594-602
Subject CollectionComputer Science
SpringerLink DateWednesday, July 11, 2007
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Design and Implementation of Rough Rules Generation from Logical Rules on FPGA Board

Akinori Kanasugi1 Contact Information and Mitsuhiro Matsumoto1 Contact Information

(1)  Department of Electronics, Tokyo Denki University, 2-2, Nishikicho, Chiyoda-ku, Tokyo 101-8457, Japan
Abstract
In this paper, the design, simulation, implementation and experiment of rough set processor are described. The experiment result shows that the proposed processor is ten times faster than PC, though the clock frequency is about 70 times lower.

Keywords  Rough sets - Processor -  FPGA

Contact Information Akinori Kanasugi
Email: kanasugi@d.dendai.ac.jp
URL: http://www.d.dendai.ac.jp/lab_site/vs/index_e.html

Contact Information Mitsuhiro Matsumoto
Email: 05gmd17@ed.cck.dendai.ac.jp
URL: http://www.d.dendai.ac.jp/lab_site/vs/index_e.html
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