Chip multiprocessing (or multiprocessor system-on-a-chip) is a technique that combines two or more processor cores on a single
piece of silicon to enhance computing performance. An important problem to be addressed in executing applications on an on-chip
multiprocessor environment is to select the most suitable number of processors to use for a given objective function (e.g.,
minimizing execution time or energy-delay product) under multiple constraints. Previous research proposed an ILP-based solution
to this problem that is based on exhaustive evaluation of each nest under all possible processor sizes. In this study, we
take a different approach and propose a pure runtime strategy for determining the best number of processors to use at runtime.
Our experiments show that the proposed approach is successful in practice.
Key words code parallelization - array-based applications - on-chip multiprocessing