An embedded pipeline/parallel architecture to support an extended quad-tree algorithm suitable for real-time estimation of the dense disparity map (DDM) for stereoscopic image processing is proposed. The system performance has been analyzed by several simulations to qualify the results by both an objective measurement (Mean Square Error) and a subjective assessment (output images). The proposed extended quad-tree is based on the block-matching algorithm, then a fine-grain granularity analysis to estimate the DDM leads us to a systolic array design for the basic Processor Element. This basic design has been utilized to the next levels quad-tree’s Processor Elements design.