A new CMOS quaternary D flip-flop is implemented employing a multiple-valued clock. PSpice simulation shows that the proposed flip-flop has correct operation. Compared with traditional multiple-valued flip-flops, the proposed multiple-valued CMOS flip-flop is characterized by improved storage capacity, flexible logic structure and reduced power dissipation.
Keywords CMOS - flip-flops - multiple-valued clock - multiple-valued logic
Supported in part by the National Natural Science Foundation of China (NSFC) under Grant No.60273093 and in part of the China-UK joint project supported by the NSFC and the Royal Society of the UK.