A fully integrated phase-locked loop (PLL) fabricated in a 0.24 m, 2.5 v digital CMOS technology is described. The PLL is intended for use in multi-gigabit-per-second clock recovery circuits in fiber-optic communication chips. This PLL first time achieved a very large locking range measured to be from 30 MHz up to 2 GHz in 0.24 m CMOS technologies. Also it has very low peak-to-peak jitter less than ±35 ps at 1.25 GHz output frequency.