With the rapid development of deep submicron (DSM) VLSI circuit designs, many issues such as time closure and power consumption are making the physical designs more and more challenging. In this review paper we provide readers with some recent progress of the VLSI physical designs. The recent developments of floorplanning and placement, interconnect effects, modeling and delay, buffer insertion and wire sizing, circuit order reduction, power grid analysis, parasitic extraction, and clock signal distribution are briefly reviewed.
This research is supported by U. S. NSF CCR-0098275 and CCR-0306298.Dian Zhou received the B.S. degree in physics and M.S. degree in electrical engineering from Fudan University, P.R. China, in 1982 and 1985, respectively, and the Ph.D. degree in electrical and computer engineering from the University of Illinois at Urbana-Champaign, in 1990. He is currently a Changjiang Honor Professor and the Dean, School of Microelectronics at Fudan University (on leave from the E.E. Department, University of Texas at Dallas). His research and teaching interests include: VLSI design, high performance VLSI circuits, telecommunication hardware and systems, mixed-signal circuits, and algorithms.
Rui-Ming Li received M.S. degree from the Department of Electrical Engineering, University of Texas at Dallas in 2001, now working toward his Ph.D. degree. He was a lecturer at the Department of Applied Mathematics, Ocean University of China before joining UTD.