In this paper we describe a parameterizable FPGA-based implementation of a sigma-delta converter used in a 96kHz audio DAC.
From specifications of the converter’s input bitwidth and data sampling frequency, VHDL generic parameters are used to automatically
generate the required design. The resulting implementation is optimized to use the minimum internal wordlength and number
of stages. We prototyped the converter on an FPGA board for verification purposes and the results are presented.