The growth of process variability in scaled CMOS requires that it is explicitly addressed in the design of high performance and low power ASICs. This growth can be attributed to multiple factors, including the difficulty of manufacturing control, the emergence of new systematic variation-generating mechanisms, and the increase in fundamental atomic-scale randomness – for example, the random placement of dopant atoms in the transistor channel. Scaling also leads to the growth of standby, or leakage power [7]. Importantly, leakage depends exponentially on threshold voltage and gate length of the device. The result is a large spread in leakage power in the presence of process variations.