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A Framework for Efficient Register Allocation through Selective Register Demotion
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A Framework for Efficient Register Allocation through Selective Register Demotion
Deepankar Bairagi5 , Santosh Pande5 and Dharma P. Agrawal5 
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Department of Electrical and Computer Engineering and Computer Science University of Cincinnati, Cincinnati, OH 45221 |
Abstract
Decisions made during register allocation greatly influence the overall quality of compiled code. Standard graph-coloring
allocators often make spilling decisions which are not guided by program structure or path-sensitive control flow information.
This can result in generation and placement of load and store instructions which is inefficient from a global perspective.
Quite often, allocation decisions get heavily influ- enced by the choice of candidates for register residency. We propose
a framework which selectively demotes variables in a contained manner to maintain balanced register pressure. The decisions
for selective demotion are made through a flow-analytic approach and the loads and stores are inserted in strategic points
such that degrading effect of spill code on overall code quality is sufficiently reduced. Our approach tries to keep variables
as candidates for register allocation only along the paths where it is profitable to do so. We attempt to identify good local
candidates for demotion, however, decisions are taken only after their global demo- tion costs are captured. We have implemented
the framework inside the SGI MIPSPRO compiler and have obtained very encouraging results in improving the allocation of a
Briggs-style allocator.
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