General transport layer protocols like TCP/IP are relatively complex because they have to deal with very different and dynamic application requirements and networking conditions. In this paper, we present an approach for hardware support of such protocols using FPGAs. We outline a hardware/software partitioning, a heterogeneous protocol engine for protocol processing acceleration and describe its transparent integration into standard systems. For the design, development and verification of such communication systems extensive simulation support is required.We describe how protocol engine VHDL models, a network simulator and existing networking applications were integrated to support this process. For this to be accomplished, object oriented techniques were applied. We present our approach for the simulation of communication systems and discuss the object structure and implementation details. As a result, the simulation enables to evaluate different configurations, modifications or the influence of system dynamics like network transmission errors on protocol processing and achievable performance.