We present a silicon-on-insulator (SOI) pass-transistor logic (PTL) gate with an active body bias control circuit and compare the proposed PTL gate with other types of PTL gates with different body bias circuits in two different 0.13
m SOI CMOS technologies. The experimental results show that the proposed SOI PTL gate using the body bias controlled technique is superior in terms of performance and power consumption than other DTMOS PTL gates.
Keywords SOI - DTMOS - pass-transistor logic - low-power - high-speed
This research was performed while Dr. Tom Chen was on sabbatical leave at HP System VLSI Technology Division, Fort Collins CO. USA.Dr. Geun Rae Cho would like to thank Hewlett-Packard Company for their generous support for this research.
Geun Rae Cho received the B.S. degree in electronics engineering from Pukyung National University, Pusan, Korea, in 1984, the M.S. degree in electronics engineering from Pusan National University, Pusan, Korea, in 1986, and the Ph.D. degree in electrical and computer engineering from the Colorado State University, Fort Collins, CO, in 2003. From 1986 to 1997, he was with Samsung Semiconductor R&D Center, where he involved in speech and audio processing chip sets, 16-bit fixed point digital signal processor, and MAC controller for fast Ethernet. His current research interests are low-power design for MPEG audio processor and OLED driver chip set.Tom Chen received a B.S. degree from Shanghai Jiao-Tong University, and a Ph.D. from the University of Edinburgh. From 1987 to 1989, Dr. Chen was with Philips Semiconductors as a member of technical staff. From 1989 to 1990, he was an assistant professor at New Jersey Institute of Technology. Since 1990, Dr. Chen has been with the Department of Electrical and Computer Engineering, Colorado State University. He is currently an associate professor. His research interests are in the areas of VLSI design and CAD methodology. He has published over 100 papers in refereed conferences and journals in the areas of VLSI system architecture and VLSI CAD methodology.